1. Field of the Invention
This invention relates to a semiconductor memory device using a silicon-on-insulator(SOI) device, and more particularly to a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.
2. Description of the Related Art
The high integration of semiconductor devices such as DRAMs goes with reduction of a cell size and in this case, it is indispensable to increase the height of a capacitor so as to assure a desired capacitance. The capacitance is inversely proportional to the distance between capacitor electrodes which are a storage node and a plate node and proportional to a dimension of the capacitor electrode and a dielectric constant of a dielectric film. Therefore, reduction of the cell dimension causes the dimension of the capacitor electrode and so as to compensate this, it should be increase the height of the capacitor electrode. However, because the capacitor is formed only in a cell region, if the height of the capacitor is increased, the topoloy between the cell region and a peripheral region is largely increased. Accordingly, it is very difficult to form contact holes in the peripheral region in the following formation of metal interconnections.
On demand for a semiconductor memory device with high performance and low power, various studies on the semiconductor memory device and circuit have been progresses. In a device aspect, the semiconductor integration technology using a single crystal substrate being comprised of bulk Si is at the limit. In stead of the bulk silicon substrate, the semiconductor integration technology using the silicon on insulator (SOI) wafer is remarked, which includes a base substrate for supporting means, a buried oxide for bonding medium and a semiconductor layer for providing a device formation region in stack. It is because the devices fabricated in the SOI wafer have advantages of high performance due to reduction of capacitance, low driving voltage due to reduction of a threshold voltage and reduction in latch-up due to complete isolation, as compared with conventional devices fabricated in the silicon substrate.
As shown in FIG. 1, a body of a transistor 10 including a channel region 3a is floated from a base substrate 1 and holes generated by impact ionization in the transistor operation do not go out of the channel region 3a but remain in the channel region 3a. Because the SOI devices cause the floating body effect such as Kink phenomenon that the peak of the drain current in the transistor 10 rapidly rises, they do not utilize in general despite the above advantage. Accordingly, the memory device fabricated in the SOI wafer has an undesired characteristic in the circuit aspect, it is applicable to fabricate the semiconductor memory device with high performance and low power.
In FIG. 1, the reference numeral 2 designates a buried oxide, 3 a semiconductor layer, 4 an isolation film, 5 a gate oxide, a gate and 7 source/drain region, respectively.
Therefore, so as to fabricate the memory device with high performance and low power using the SOI wafer, it should solve the problem due to topology between the cell region and the peripheral region and the problem due to the floating body effect.